(1) Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof. More specifically, the present invention relates to a semiconductor nonvolatile memory device having a floating gate (charge storing layer) and a control gate where a source region has a low resistance or a semiconductor nonvolatile memory device having a structure (tunnel insulating film/Si3N4 film or Al2O3 film/oxide film/control gate film) where an Si3N4 layer or an Al2O3 layer is used to store charges instead of the floating gate, and a manufacturing method thereof.
(2) Description of the Related Art
For example, JP-A 2000-216270 discloses a structure of and a manufacturing method of a conventional semiconductor nonvolatile memory device (flash memory). This semiconductor nonvolatile memory device will be described with reference to FIGS. 24 to 29. First, with reference to FIGS. 24(a) to 24(d), trenches are formed in stripes in a surface of a silicon substrate 100 by means of reactive etching. Each trench is filled with an element isolation insulating film 101 made of SiO2 to provide active regions (diffusion layer regions) 102 between respective element isolation insulating films 101. Herein, FIGS. 24(a) to 24(d) illustrate a first step of the manufacturing method of the conventional semiconductor nonvolatile memory device. FIG. 24(a) is a partial plan view, FIG. 24(b) is a cross-sectional view taken along line I-I of FIG. 24(a), FIG. 24(c) is a cross-sectional view taken along line II-II of FIG. 24(a), and FIG. 24(d) is a cross-sectional view taken along line III-III of FIG. 24(a).
Next, with reference to FIGS. 25(a) to 25(d), a gate oxide film 103 made of SiO2 and a floating gate film (hereinafter, referred to as “FG electrode”) 104 made of polysilicon are sequentially layered on the entire surface of the silicon substrate 100. A resist film (not shown) is formed thereon using a photolithographic method so as to cover the active regions 102. The gate oxide film 103 and the FG electrode 104 are pattered in stripes by means of etching using the resist film as a mask. Herein, FIGS. 25(a) to 25(d) illustrate a second step of the manufacturing method of the conventional semiconductor nonvolatile memory device. FIG. 25(a) is a partial plan view, FIG. 25(b) is a cross-sectional view taken along line I-I of FIG. 25(a), FIG. 25(c) is a cross-sectional view taken along line II-II of FIG. 25(a), and FIG. 25(d) is a cross-sectional view taken along line III-III of FIG. 25(a).
Next, with reference to FIGS. 26(a) to 26(d), an interlayer insulating film (so-called ONO film) 105 including a silicon oxide film, a silicon nitride film and a silicon oxide film is formed to cover the FG electrode 104. Next, plural control gates (hereinafter, referred to as CG wires) 106 are formed on the upper surface of the silicon substrate 100 in a direction orthogonal to a longitudinal direction of the element isolation insulating films 101. Each CG wire 106 is formed of a layered film including a lower layered polycrystal silicon film 106a and an upper layered WSi film 106b. Herein, FIGS. 26(a) to 26(d) illustrate a third step of the manufacturing method of the conventional semiconductor nonvolatile memory device. FIG. 26(a) is a partial plan view, FIG. 26(b) is a cross-sectional view taken along line I-I of FIG. 26(a), FIG. 26(c) is a cross-sectional view taken along line II-II of FIG. 26(a), and FIG. 26(d) is a cross-sectional view taken along line III-III of FIG. 26(a).
Next, with reference to FIGS. 27(a) to 27(d), a resist pattern 107 having openings in source formation regions between the CG wires 106 is formed. Thereafter, this resist pattern 107 (hatched portions in FIG. 27(a)) and the CG wires 106 are used as a mask to etch the element isolation insulating films 101, thereby exposing the surfaces of the trenches 100a (bottom face 10b and both side faces 100c, 100c), i.e., the surface of the silicon substrate 100. Herein, FIGS. 27(a) to 27(d) illustrate a fourth step of the manufacturing method of the conventional semiconductor nonvolatile memory device. FIG. 27(a) is a partial plan view, FIG. 27(b) is a cross-sectional view taken along line I-I of FIG. 27(a), FIG. 27(c) is a cross-sectional view taken along line II-II of FIG. 27(a), and FIG. 27(d) is a cross-sectional view taken along line III-III of FIG. 27(a).
Next, with reference to FIGS. 28(a) to 28(d), arsenic ions are implanted as impurities in a direction perpendicular to the plane of the silicon substrate 100, and source diffusion layers 108 are formed in the regions between the respective trenches 100a (active regions 102) and at the bottom face 100b of the respective trenches 100a in the exposed source formation regions. Next, after the resist pattern 107 is removed, arsenic ions are implanted into the entire surface of the silicon substrate 100 using the CG wires 106 as a mask so as to form the source diffusion layers 108 and drain diffusion layers 109. Herein, FIGS. 28(a) to 28(d) illustrate a fifth step of the manufacturing method of the conventional semiconductor nonvolatile memory device. FIG. 28(a) is partial a plan view, FIG. 28(b) is a cross-sectional view taken along line I-I of FIG. 28(a), FIG. 28(c) is a cross-sectional view taken along line II-II of FIG. 28(a), and FIG. 28(d) is a cross-sectional view taken along line III-III of FIG. 28(a). In addition, plural arrow marks indicate ion implantation in FIGS. 28(c) and 28(d).
Next, with reference to FIGS. 29(a) to 29(d), an insulating film such as a silicon oxide film is made to grow on the entire surface of the silicon substrate 100 and etching back is carried out, so that sidewall insulating films 110 are formed on both side faces of the respective layered bodies including the CG wires 106, the interlayer insulating films 105, the FG electrodes 104 and the gate oxide films 103. Next, the silicon substrate 100 on a turn table is rotated, and a rotation oblique ion implantation of arsenic ions is carried out on the entire surface of the silicon substrate 100. Arsenic ions are implanted into the both side faces 100c, 100c of the trenches 100a so as to form the source diffusion layers 108. As a result, ion implantation for the surfaces of the active regions 102, the bottom face 100 and both side faces 100c, 100c of the trenches 100a are completed, thereby achieving reduction in resistance of the source regions. Thereafter, a wire isolation film (not shown) is formed on the entire surface of the silicon substrate 100 according to the known art, and this wire isolation film is pattered so as to form contact portions (not shown) in the source diffusion layers 108 and drain diffusion layers 109 in such a manner that pairs of two FG electrodes 104 on both sides of each source diffusion layer 108 are divided from each other. Next, a metal wire film (not shown) is deposited according to a sputtering method, and this metal wire film is patterned in a photolithographic step and in a etching step to obtain a flash memory. Herein, FIGS. 29(a) to 29(d) illustrate a sixth step of the manufacturing method of the conventional semiconductor nonvolatile memory device. FIG. 29(a) is a partial plan view, FIG. 29(b) is a cross-sectional view taken along line I-I of FIG. 29(a), FIG. 29(c) is a cross-sectional view taken along line II-II of FIG. 29(a), and FIG. 29(d) is a cross-sectional view taken along line III-III of FIG. 29(a). In addition, plural arrow marks indicate the diagonal ion implantation through rotation in FIGS. 29(c) and 29(d).
In the step (see FIG. 27(c)) described with reference to FIG. 27, however, the element isolation insulating films in the source formation regions are removed from the silicon substrate 100 so that the surfaces of the trenches 100a are exposed. Consequently, steps are formed in the surface of the silicon substrate 100. Therefore, as shown in FIG. 29, in the conventional method for forming diffusion layers by using a method for rotation oblique ion implantation, when memory cells are miniaturized, an implantation angle θ at which ions can be implanted into the side faces of the trenches B is limited due to shadowing effects as shown in FIG. 30, and the resistance in the diffusion layer that is equivalent to that of the active region surfaces A cannot be secured even in the case where rotation oblique ion implantation carried out on the side faces B. As a result, it is difficult to lower the resistance in the source regions to 5000Ω or less (standard of a source resistance value that does not cause a problem in the speed of operation). Consequently, a problem arises where deterioration is caused in the operation of cells in the flash memory as a device, specifically, in a writing speed and in a reading speed.
As shown in FIG. 31, an implantation angle θ that is required to implant ionic species into a lower part of the side faces of the trenches cannot be made to be about 39° or more due to the shadowing effects caused by a structure of the trench where, for example, a width L of the element isolation between memory cells is 0.25 μm, a depth h of the trench is 0.26 μm and a taper angle θ1 is 80°. In the case where ions are implanted at an implantation angle θ of 39°, a resistance in the diffusion layer becomes about 10000Ω, which is a high diffusion resistance. It is necessary to implant the same amount of ions as those in the active region surfaces A and the bottom faces of the trenches C (see FIG. 30) in the side faces of the trenches B, in order to lower the diffusion resistance. It is therefore necessary to implant ions approximately perpendicularly to the side faces of the trenches B. In FIG. 31, an orbit of implanted ionic species (at an implantation angle of 39°) is indicated by a solid line arrow mark, and an ideal orbit for implanted ionic species (at an implantation angle of 80°) is indicated by a dotted line arrow mark.
Also in FIG. 31, “a” indicates a gradient length in the side face of the trench having a taper angle θ1, “b” indicates a width of the bottom face of the trench, and “θ2” indicates an angle formed between an orbit of implanted ionic species and the bottom face of the trench.
The above-mentioned “a”, “b” and “θ2” can be found by the following equations:a=h/tan θ1,a+b=h/tan θ2, andθ2=tan−1(h/(L−(a+b))) or 90°−θ.
In the case of a semiconductor substrate having the structure shown in FIG. 31, “a”=0.046 μm, “θ2”=51° and “b”=0.206 μm according to the above-mentioned equations.
However, the width b of the bottom face of the trench must be 1.43 μm or more, which is not desirable for memory cell miniaturization, in a trench where the depth h of the trench is 0.26 μm and the taper angle θ1 is 80°, as shown in FIG. 32, in order to implant ions in the ideal orbit of implanted ions (implantation angle is 80°). Therefore, another technique is considered, where the depth of the trench is decreased so as to be 0.2 μm or less, and the resistance in the diffusion layer in the side faces of the trench B which is the source region is lowered in order to lower the resistance in the diffusion layer and miniaturize the memory cell. In the case where the depth of the trench is reduced so as to be 0.2 μm or less, however, withstand voltage of the element isolation in a peripheral transistor portion is not sufficient (0.2 μm or more is necessary). Therefore, it becomes necessary to prepare trenches with different depths within memory cells and in the peripheral transistor portion, which increases the number of steps in the process, adding, for example, a photolithographic step of forming a mask, and a new problem arises where the cost of the process increases.